The invention relates to microcomputers and computer systems.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network including for example connection to a host microcomputer for use in debugging routines. Such systems are known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on-chip it is common for bit packets to be transmitted between modules on a chip in a bit parallel format along an on-chip bus. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Furthermore unwanted CPU execution cycles occur when CPU operation is required to respond to each packet on the on-chip bus.
It is an object of the present invention to provide an improved microcomputer, and an improved method of operating a microcomputer system, in which external communications are simplified and bit packets, which may be obtained from locations off-chip, are more efficiently responded to on-chip.
The invention provides a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between said CPU and at least one other module with logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said module being operable to receive the packet and respond thereto independently of operation of the CPU, said integrated circuit device further comprising an external communication port connected to said bus, said port having an internal signal connection to said bus, said internal connection having an internal parallel format, an external signal connection having an external format less parallel than said internal format, and translation circuitry to effect conversion of digital signal packets between said internal and external format, said input port being operable independently of operation of said CPU.
Preferably said translation circuitry is arranged to translate bit packets between an on-chip bit parallel format and an external bit serial format.
Preferably said on-chip CPU includes circuitry for generating bit packets including a destination identifier within each packet, said translation circuitry being operable to translate packets between said internal and external formats while retaining identification of said destination.
Preferably said packets comprise request packets for sending from a packet source to a destination, said source and destination being both connected to said communication bus, and response packets for return from a said destination to said source.
Said single integrated circuit chip may have a plurality of CPUs on the same chip each connected to said communication bus wherein each CPU on said chip may address said external port.
Preferably the or each on-chip CPU has a first memory local to the CPU, and an external computer device is connected to said external communication port, said external computer device having a second memory local to the external computer device.
The invention includes a method of operating a computer system comprising a microprocessor on a single integrated circuit chip with an on-chip CPU, a plurality of registers, a communication bus providing a parallel communication path between said CPU and at least one other module with logic circuitry connected to said bus, and an external communication port connected to said bus, said method comprising generating on said bus digital signal packets including control bits, receiving at said module a packet on the bus and responding thereto independently of operation of the CPU, said method further comprising supplying to said external port a packet having an internal parallel format, and translating the packet in the port independently of operation of the CPU to an external format less parallel than said internal format.
Preferably bit packets are generated including a destination identifier and the translation in said external port translates bit packets between said internal and external formats while retaining identification of the destination.
Preferably said bit packets comprise request packets sent from a packet source to a destination via said bus, and response packets returned from said destination to a source of the request packet.
Preferably at least some of said bit packets include in addition to said destination identifier an address identifier for use within a module forming the destination.
Preferably control circuitry decodes destination identifiers within said packets and controls supply of the packets to modules in accordance with the decoded destination.
Preferably said control circuitry provides control signals along dedicated signal paths to each module to control access between each module and said bus in dependence on operation of the decode circuitry.
A plurality of CPUs may be provided on the same chip and each may communicate via said bus with said external port.
The or each on-chip CPU may address memory local to said integrated circuit device or, through said external port, memory local to said external computer device.